1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a plurality of memory cells which need refreshing of storage data within a prescribed time. The invention more particularly relates to a structure for refreshing in a multi-bank semiconductor memory device which has a plurality of memory banks and needs the refresh operation.
2. Description of the Background Art
In order to implement high-speed data transfer between a processing device such as a CPU (Central Processing Unit) and a DRAM (Dynamic Random Access Memory) as a main memory, a synchronous semiconductor memory device is used which inputs/outputs data in synchronization with a clock signal which is, for example, a system clock.
FIG. 16 shows states of external signals for a synchronous DRAM (SDRAM) which is one of conventional synchronous semiconductor memory devices. Referring to FIG. 16, in the SDRAM, an operation mode is determined by the combination of the states of respective external control signals /CS, /RAS, /CAS and /WE at the rising edge of an external clock signal CLK. In clock cycle #1, when chip selection signal /CS and row address strobe signal /RAS are set at L level, and the column address strobe signal /CAS and write enable signal /WE are set at H level at the rising edge of clock signal CLK, an active command is supplied and an operation for activating a memory cell array, that is, the row selecting operation, is carried out in the SDRAM. The row selection is carried out using an address signal ADD which is supplied simultaneously with the active command as a row address signal.
In clock cycle #3, when chip selection signal /CS and the column address strobe signal /CAS are set at L level and row address strobe signal /RAS and write enable signal /WE are set at H level at the rising edge of clock signal CLK, a read command of instructing reading of data is supplied. When the read command is supplied, an operation of selecting a memory cell column is carried out using address signal ADD which is applied currently as a column address signal, and data in a selected memory cell is read out. Since the SDRAM has a period referred to as CAS latency, read data Q attains a defined state after the period of the CAS latency. In the case shown in FIG. 16, the CAS latency is 1, so that read data Q attains a defined state at the rising edge of clock signal CLK in clock cycle #4. In the SDRAM, the read command is supplied to read out data of the number referred to as a burst length consecutively in each clock cycle using an address which is supplied simultaneously with the read command as a leading address. FIG. 16 shows a case in which data is read out with the burst length being 1.
In clock cycle #5, when chip selection signal /CS, column address strobe signal /CAS and write enable signal /WE are set at L level and row address strobe signal /RAS is set at H level, a write command of instructing writing of data is supplied. When the write command is supplied, a memory cell is selected using address signal ADD supplied currently as a column address, and data is written into a selected memory cell. When data is to be written, write data D is externally supplied simultaneously with the write command and taken into the SDRAM. Write data D which is taken therein is internally written into the selected memory cell at a prescribed timing. At the time of the data writing, data of the number of the burst length can also be written consecutively.
In the SDRAM, when the active command is supplied, the array attains an active state. In order to set the active array into a non-selected state, that is, a precharge state, chip selection signal /CS, row address strobe signal /RAS and write enable signal /WE are set at L level and the column address strobe signal /CAS is set at H level, and a precharge command is supplied in clock cycle #7. When the precharge command is given, the memory array which has been set in a selected state by the active command returns to the precharge state, and an internal selected row returns to the non-selected state.
In the SDRAM, a memory cell includes a capacitor which stores information therein as in a normal DRAM. Since the information stored in the capacitor needs to be refreshed within a prescribed period, chip selection signal /CS, row address strobe signal /RAS and write enable signal /WE are set at L level and column address strobe signal /CAS is set at H level in clock cycle #9. Accordingly, an auto-refresh command is supplied to automatically refresh a memory array. When the auto-refresh command is supplied, a refresh address which designates a memory cell to be refreshed is internally generated, data in the memory cell is refreshed according to the refresh address, and the memory array returns to the precharge state after the refresh completes.
As shown in FIG. 16, control signals are externally supplied synchronously with clock signal CLK, so that the internal operation starting timing can be determined using the rising edge of clock signal CLK as trigger. As a result, there is no need to consider a margin for internal operation timing which is necessary because of the skew or the like in the external control signals, and high-speed internal operation is implemented.
FIG. 17 schematically shows an internal configuration of a conventional SDRAM. Referring to FIG. 17, the SDRAM SD includes a plurality of memory banks BK0-BKn, and a data input/output buffer DB which is coupled commonly to memory banks BK0-BKn and inputs/outputs data. Each of memory banks BK0-BKn can be driven into active/inactive state regardless of the active/inactive state of other memory banks. For example, when memory bank BK0 is in the active state and a memory cell row is in the selected state, memory bank BK1 may be driven into the active state to drive a memory cell row into the selected state, and the memory cell row in the selected state may be driven into the non-selected state or the precharge state (inactive state).
The read command and the write command are supplied together with a bank address which designates a memory bank. Data can be input/output via data input/output buffer DB to/from the memory bank designated by the bank address. Therefore, at the time of access to one memory bank, other memory banks can be activated/inactivated to be sequentially accessed. Even at the time of page switching (to select a different word line), the memory array does not need to be set in the precharge state, so that data can be externally accessed consecutively. In particular, when data in a prescribed small area on a display screen is to be accessed in image processing, if memory banks BK0-BKn are configured to store pixel data on different scanning lines on the screen, data in the small area can be accessed at high-speed. In addition, when memory banks BK0-BKn are simultaneously set in the selected state, memory banks BK0-BKn can be utilized as the secondary cache, resulting in reduction of the penalty at the time of the cache miss.
FIG. 18 shows an entire configuration of the semiconductor memory device shown in FIG. 17 in detail. FIG. 18 presents a configuration having four banks as one example.
With reference to FIG. 18, the semiconductor memory device includes array banks 1a, 1b, 1c and 1d that can be driven into the active/inactive state independently of each other. The active state here represents a state in which a word line is selected in an array and a sense amplifier latches memory cell data, and the inactive state represents a state in which all word lines are in the non-selected state, the sense amplifier is in the inactive state, and each bit line of a bit line pair is precharged at a prescribed voltage level. Each of the array banks 1a-1d has the same configuration, and FIG. 18 shows the configuration of array bank 1a. Array bank 1a includes a memory array 1aa having a plurality of memory cells MCs arranged in rows and columns, and a row-related peripheral circuit 1ab which carries out an operation related to row selection in memory array 1aa. A word line WL is arranged corresponding to each row of memory cells MC, and a bit line pair BLP is arranged corresponding to each column of memory cells MC. FIG. 18 representatively shows one word line WL, one bit line pair BLP, and a memory cell MC placed at the crossing of them.
Row-related peripheral circuit 1ab includes a sense amplifier circuit provided to each bit line pair BLP, for differentially amplifying the potential of a corresponding bit line pair when activated, a bit line precharge circuit which precharges each bit line pair BLP to a prescribed potential level and others.
Bank drive circuits 2a, 2b, 2c and 2d for activating/inactivating corresponding array banks, as well as row address latches 3a, 3b, 3c and 3d are provided respectively to array banks 1a-1d. Each of bank drive circuits 2a-2d has the same configuration, and FIG. 18 shows a configuration of bank drive circuit 2a. Bank drive circuit 2a includes a row-related control circuit 2aa which controls an operation of row-related peripheral circuit 1ab of the corresponding array bank 1a according to a bank activation signal ACT0 from a bank activation control circuit 4, and a row selection circuit 2ab which decodes a row address signal RA0 supplied from a corresponding row address latch 3a and drives an addressed word line in corresponding memory array 1aa into the selected state according to the result of the decoding under the control by row-related control circuit 2aa. Row selection circuit 2ab includes a row decoder, and a word line drive circuit which drives an addressed word line into the selected state according to an output signal from the row decoder.
Row address latches 3a-3d each having a configuration described later in detail take in an address signal supplied according to a bank designation signal from bank activation control circuit 4, and latch and output the address signal. Operations of bank drive circuits 2a-2d and row address latches 3a-3d are controlled independently of each other under the control by bank activation control circuit 4.
Bank activation control circuit 4 receives an operation mode instruction signal from a command decoder 5 and a bank address signal BAi from an address buffer 6, and generates a control signal according to the operation mode instruction supplied from command decoder 5 for only a bank designated by bank address signal BAi. FIG. 18 exemplarily shows a configuration in which bank activation signals ACT0, ACT1, ACT2 and ACT3 are supplied from bank activation control circuit 4 to bank drive circuits 2a, 2b, 2c and 2d respectively. Bank activation control circuit 4 controls activation/inactivation of the bank activation signal according to an array activating instruction signal .phi.a and a precharge instruction signal .phi.p from command decoder 5 and bank address signal BAi from address buffer 6.
Command decoder 5 decodes signals supplied from a control signal input buffer 7 which in turn takes at the rising edge of clock signal CLK the signals /CS, /RAS, /CAS and /WE externally applied in synchronization with clock signal CLK, and generates the operation mode instruction signal according to the states of these signals. In some cases, command decoder 5 additionally uses a specific address signal bit supplied from address buffer 6 (the path is not shown) in order to generate the operation mode instruction signal. (This process is described later.)
Address buffer 6 takes externally supplied address signal AD and a bank address signal BA synchronously with the rising edge of clock signal CLK, and generates an internal address signal ADi and an internal bank address signal BAi.
The semiconductor memory device further includes a refresh control circuit 8 which generates a control signal necessary for the refresh according to a refresh mode instruction signal .phi.r from command decoder 5 to execute the refresh operation, a refresh counter 19 which generates a refresh address designating a memory cell to be selected and refreshed under control by refresh control circuit 8, and a multiplexer 10 which selects either internal address signal ADi from address buffer 6 or the refresh address from refresh counter 9 and supplies the selected one to row address latches 3a-3d under the control by refresh control circuit 8.
Refresh control circuit 8 supplies bank activation control circuit 4 with a control signal necessary for the refresh operation when refresh instruction signal .phi.r is supplied from command decoder 5. In the refresh mode, all memory array banks 1a--1a carry out the refresh operation via bank activation control circuit 4. Now, with reference to the timing chart shown in FIG. 19, an operation at the time of the refresh of the semiconductor memory device shown in FIG. 18 is described.
In clock cycle #0, row address strobe signal /RAS and chip selection signal /CS are set at L level and column address strobe signal /CAS and write enable signal /WE are set at H level, and an active command is supplied. When command decoder 5 receives the active command, command decoder 5 generates array activating instruction signal .phi.a and supplies it to bank activation control circuit 4. When bank activation control circuit 4 receives array activating instruction signal .phi.a, bank activation control circuit 4 supplies a latch instruction signal to a row address latch corresponding to a designated array bank according to bank address signal BAi supplied from address buffer 6, and drives array activation signal ACT for a corresponding bank drive circuit into the active state.
Multiplexer 10 has selected internal address signal ADi supplied from address buffer 6, and a row address latch provided corresponding to an array bank designated by the bank address takes the internal address signal supplied via multiplexer 10 and generates an internal row address signal RA. Accordingly, a bank drive circuit corresponding to an addressed bank is activated, and the row selecting operation is carried out in the designated bank.
Since the bank in the active state should be driven into the inactive state for the refresh operation, signals /CS, /RAS and /WE are set at L level and column address strobe signal /CAS is set at H level in clock cycle #3, and a precharge command is supplied. When the precharge command is supplied, command decoder 5 generates precharge instruction signal .phi.d and supplies it to bank activation control circuit 4. For the precharge command, two kinds of precharge commands are supported. One is a single precharge command for returning only one bank to the precharge state, and the other is an all-bank precharge command for returning all banks to the precharge state simultaneously. The single precharge command and all-bank precharge command are set respectively by the H level and L level of a specific bit (bit A10 for example) of address signal AD. The precharge command causes the bank activation signal ACT for a bank in the active state to be driven into L level of the inactive state, and array banks 1a-1d return to the precharge state under the control by bank drive circuits 2a-2d respectively.
After an elapse of the clock cycles necessary for the precharge operation, chip selection signal /CS, row address strobe signal /RAS and the column address strobe signal /CAS are set at L level, and write enable signal /WE is set at H level in clock cycle #6. Command decoder 5 determines that a refresh command is supplied, according to the states of signals supplied from control signal input buffer 7, and generates refresh instruction signal .phi.r for application to refresh control circuit 8. Refresh control circuit 8 starts refresh counter 9 according to refresh instruction signal .phi.r and causes refresh counter 9 to generate a refresh address, and causes multiplexer 10 to select the refresh address from refresh counter 9.
Bank activation control circuit 4 drives array activation signals ACT0-ACT3 into the active state to activate all banks under the control signal from refresh control circuit 7. Accordingly, the refresh address from refresh counter 9 is latched in row address latches 3a-3d, bank drive circuits 2a-2d all operate, and memory cells of a row designated by the refresh address are refreshed in each of array banks 1a-1d. At the time of the refresh operation, array activation signals ACT0-ACT3 are driven into the active state only for a prescribed period. After an elapse of the prescribed period, array activation signals ACT0-ACT3 return to the inactive state. In clock cycle #9 in FIG. 19, array activation signals ACT0-ACT3 are driven into the inactive state. Accordingly, all banks can be refreshed, and storage data can be refreshed periodically.
FIG. 20 schematically shows a configuration of a processing system using the SDRAM. With reference to FIG. 20, SDRAM SD is connected to a memory controller MCT via a memory bus 11. Memory controller MCT is connected to a processor PU via a system bus 13. Memory controller MCT is also connected to a bank management memory BMM. Memory controller MCT causes processor PU to wait and sets processor PU in a waiting state via system bus 13 at an interval of a prescribed time. In this state, memory controller MCT issues a refresh instruction to SDRAM SD. In the normal access mode, memory controller MCT stores information on whether a bank is active or inactive as well as a bank row address indicating a selected row address of a bank in the active state in bank management memory BMM for each of the banks, and constantly manages the states of the respective banks in SDRAM SD.
After memory controller MCT carries out the refresh for SDRAM SD via memory bus 11, memory controller MCT returns SDRAM SD to a state before the refresh, referring to bank management memory BMM. In other words, memory controller MCT supplies an active command for a bank in the active state together with its row address. After the state of SDRAM SD is recovered, memory controller MCT allows processor PU to make an access. Therefore, processor PU cannot access SDRAM SD not only during the period in which the refresh is carried out for SDRAM SD, but also during the period from completion of the refresh to the time when SDRAM SD is returned to its original state, and the penalty due to the refresh increases.
In order to return SDRAM SD back to its original state after the refresh is completed, clock cycles equivalent in number to banks that are in the active state when the refresh instruction is supplied are necessary. It is because the active command is supplied together with only one bank address at a time, that is, the active command is supplied only to one bank at a time. Consequently, if the storage capacity of SDRAM SD as well as the number of its array banks increase, the number of clock cycles in which processor PU is caused to be in the waiting state at the time of the refresh increases, and the penalty for the refresh increases. In other words, when the refresh is carried out, processor PU cannot access SDRAM SD and is caused to be in the waiting state. As a result, an advantage of the bank configuration of SDRAM SD that sequentially activation of the banks allows accessing with no influence of a precharge time at the time of page switching of a bank is lost.
In addition, memory controller MCT stores information concerning states of respective banks in SDRAM SD in bank management memory BMM. If the number of banks in SDRAM SD increases, the capacity of bank management memory BMM also increases, so that a load for managing the state of each bank by memory controller MCT also increases.
An SDRAM having no bank also requires, after the refresh, a memory to be returned back to a state before the refresh under the control by an external memory controller. As a result, the SDRAM having no bank also has a problem of an increased load of the external memory controller after the refresh is completed.